;This is a device fuse description file for avrsp.exe. Placing this file
;with avr?p(x).exe will able to help recognizing the read fuse bits.
;-----------------------------------------------------------------------------;
Device: AT90S1200
Mode: Parallel
Low: --5----0
       |    +-- RCEN (1:External CLK, 0:Internal CLK)
       +-- SPIEN (1:Disable ISP, 0:Enable ISP)

;-----------------------------------------------------------------------------;
Device: AT90S2313
Device: AT90S4414
Device: AT90S8515
Mode: Parallel
Low: --5----0
       |    +-- FSTRT (1:Slow start, 0:Fast start)
       +-- SPIEN (1:Disable ISP, 0:Enable ISP)

;-----------------------------------------------------------------------------;
Device: AT90S4434
Device: AT90S8535
Mode: ISP/Parallel
Low: --5----0
       |    +-- FSTRT (1:Slow start, 0:Fast start)
       +-- SPIEN (1:Disable ISP, 0:Enable ISP) *Available only parallel mode

;-----------------------------------------------------------------------------;
Device: AT90S2333
Device: AT90S4433
Mode: ISP/Parallel
Low: --543210
       |||+++-- CKSEL[2:0] Clock source selection
       ||+-- BODEN (1:Disable BOD, 0:Enable BOD)
       |+-- BODLEVEL (1:2.7V, 0:4.0V)
       +-- SPIEN (1:Disable ISP, 0:Enable ISP) *Available only parallel mode

;-----------------------------------------------------------------------------;
Device: AT90S2323
Mode: ISP/HVS
Low: --5----0
       |    +-- FSTRT (1:Slow start, 0:Fast start)
       +-- SPIEN (1:Disable ISP, 0:Enable ISP) *Available only HVS mode

;-----------------------------------------------------------------------------;
Device: AT90S2343
Mode: ISP/HVS
Low: --5----0
       |    +-- RCEN (1:External CLK, 0:Internal CLK)
       +-- SPIEN (1:Disable ISP, 0:Enable ISP) *Available only HVS mode

;-----------------------------------------------------------------------------;
Device: ATtiny10
Device: ATtiny11
Mode: HVS
Low: ---43210
        ||+++-- CKSEL[2:0] Clock source selection
        |+-- RSTDISBL (1:Use RESET pin, 0:Disable RESET(used as PB5))
        +-- FSTRT (1:Slow start, 0:Fast start)

;-----------------------------------------------------------------------------;
Device: ATtiny12
Mode: ISP/HVS
Low: 76543210
     ||||++++-- CKSEL[3:0] Clock source selection
     |||+-- RSTDISBL (1:Use RESET pin, 0:Disable RESET(used as PB5))
     ||+-- SPIEN (1:Disable ISP, 0:Enable ISP)
     |+-- BODEN (1:Disable BOD, 0:Enable BOD)
     +-- BODLEVEL (1:1.8V, 0:2.7V)

;-----------------------------------------------------------------------------;
Device: ATtiny15
Mode: ISP/HVS
Low: 7654--10
     ||||  ++-- CKSEL[1:0] Clock source selection
     |||+-- RSTDISBL (1:Use RESET pin, 0:Disable RESET(used as PB5))
     ||+-- SPIEN (1:Disable ISP, 0:Enable ISP)
     |+-- BODEN (1:Disable BOD, 0:Enable BOD)
     +-- BODLEVEL (1:2.7V, 0:4.0V)

;-----------------------------------------------------------------------------;
Device: ATtiny22
Mode: ISP/HVS
Low: --5----0
       |    +-- RCEN (1:External CLK, 0:Internal CLK)
       +-- SPIEN (1:Disable ISP, 0:Enable ISP) *Available only HVS mode

;-----------------------------------------------------------------------------;
Device: ATtiny13
Mode: ISP/HVS
Low: 76543210
     ||||||++-- CKSEL[1:0] Clock selection
     ||||++-- SUT[1:0] Startup time selection
     |||+-- CKDIV8 Clock division ratio (1:1/1, 0:1/8)
     ||+-- WDTON (1:WDT normal, 0:WDT always on)
     |+-- EESAVE (Retain EEPROM at chip erase 1:No, 0:Yes)
     +-- SPIEN (1:Disable ISP, 0:Enable ISP) *Available only HVS mode

High:---43210
        ||||+-- RSTDISBL (RESET pin 1:Enable, 0:Disable(PB5))
        ||++-- BODLEVEL[1:0] (BOD 11:None, 10:1.8V, 01:2.7V, 00:4.3V)
        |+-- DWEN (On-Chip Debugging via RESET pin 1:Disable, 0:Enable)
        +-- SPMEN (SPM instruction 1:Disable, 0:Enable)

;-----------------------------------------------------------------------------;
Device: ATtiny25
Device: ATtiny45
Device: ATtiny85
Device: ATtiny24
Device: ATtiny44
Device: ATtiny84
Mode: ISP/HVS
Low: 76543210
     ||||++++-- CKSEL[3:0] Clock source selection
     ||++-- SUT[1:0] Startup time selection
     |+-- CKOUT (0:Output system clock on the CLKO pin)
     +-- CKDIV8 Clock division ratio (1:1/1, 0:1/8)

High:76543210
     |||||+++-- BODLEVEL[2:0] (111:Off, 110:1.8, 101:2.7, 100:4.3, 011:2.3, 010:2.2, 001:1.9, 000:2)
     ||||+-- EESAVE (Retain EEPROM at chip erase 1:No, 0:Yes)
     |||+-- WDTON (1:WDT normal, 0:WDT always on)
     ||+-- SPIEN (1:Disable ISP, 0:Enable ISP) *Available only HVS mode
     |+-- DWEN (On-Chip Debugging via RESET pin 1:Disable, 0:Enable)
     +-- RSTDISBL (RESET pin 1:Enable, 0:Disable(PORT))

High:-------0
            +-- SELFPRGEN *Refer to data sheet

;-----------------------------------------------------------------------------;
Device: ATtiny2313
Mode: ISP/Parallel
Low: 76543210
     ||||++++-- CKSEL[3:0] Clock source selection
     ||++-- SUT[1:0] Startup time selection
     |+-- CKOUT (0:Output system clock on the CLKO pin)
     +-- CKDIV8 Clock division ratio (1:1/1, 0:1/8)

High:76543210
     |||||||+-- RSTDISBL (RESET pin 1:Enable, 0:Disable(PA2))
     ||||+++-- BODLEVEL[2:0] (111:Off, 110:1.8, 101:2.7, 100:4.3)
     |||+-- WDTON (1:WDT normal, 0:WDT always on)
     ||+-- SPIEN (1:Disable ISP, 0:Enable ISP) *Available only in Parallel mode
     |+-- EESAVE (Retain EEPROM at chip erase 1:No, 0:Yes)
     +-- DWEN (On-Chip debugging via RESET pin 1:Disable, 0:Enable)

Ext: -------0
            +-- SPMEN (SPM instruction 1:Disable, 0:Enable)

;-----------------------------------------------------------------------------;
Device: ATtiny26
Mode: ISP
Low: 76543210
     ||||++++-- CKSEL[3:0] Clock source selection
     ||++-- SUT[1:0] Startup time
     |+-- CKOPT (36pF between PB4-GND  1:Disabled, 0:Enabled)
     +-- PLLCK *Refer to data sheet

High:---43210
        ||||+-- BODEN (1:Disable BOD, 0:Enable BOD)
        |||+-- BODLEVEL (1:2.7V, 0:4.0V)
        ||+-- EESAVE (Retain EEPROM at chip erase 1:No, 0:Yes)
        |+-- SPIEN (1:Disable, 0:Enable) *Available only in Parallel mode
        +-- RSTDISBL (1:Use RESET pin, 0:Disable RESET(used as PB7))

;-----------------------------------------------------------------------------;
Device: ATtiny261
Device: ATtiny461
Device: ATtiny861
Mode: ISP/Parallel
Low: 76543210
     ||||++++-- CKSEL[3:0] Clock source selection
     ||++-- SUT[1:0] Startup time selection
     |+-- CKOUT (0:Output system clock on the CLKO pin)
     +-- CKDIV8 Clock division ratio (1:1/1, 0:1/8)

High:76543210
     |||||+++-- BODLEVEL[2:0] (111:Off, 110:1.8, 101:2.7, 100:4.3)
     ||||+-- EESAVE (Retain EEPROM at chip erase 1:No, 0:Yes)
     |||+-- WDTON (1:WDT normal, 0:WDT always on)
     ||+-- SPIEN (1:Disable ISP, 0:Enable ISP) *Available only HVS mode
     |+-- DWEN (On-Chip Debugging via RESET pin 1:Disable, 0:Enable)
     +-- RSTDISBL (RESET pin 1:Enable, 0:Disable(PORT))

High:-------0
            +-- SELFPRGEN *Refer to data sheet

;-----------------------------------------------------------------------------;
Device: ATtiny28
Mode: Parallel
Low: ---43210
        |++++-- CKSEL[3:0] Clock source selection
        +-- INTCAP (1:Disable CAP, 0:Enable CAP)

;-----------------------------------------------------------------------------;
Device: ATmega161
Mode: ISP/Parallel
Low: -6543210
      ||||+++-- CKSEL[2:0] Clock source selection
      |||+-- BODEN (1:Disable BOD, 0:Enable BOD)
      ||+-- BODLEVEL (1:2.7V, 0:4.0V)
      |+-- SPIEN (1:Disable ISP, 0:Enable ISP) *Available only in Parallel mode
      +-- BOOTRST *Refer to data sheet

;-----------------------------------------------------------------------------;
Device: ATmega162
Mode: ISP/Parallel
Low: 76543210
     ||||++++-- CKSEL[3:0] Clock source selection
     ||++-- SUT[1:0] Startup time
     |+-- CKOUT (0:Output system clock on the CLKO pin)
     +-- CKDIV8 Clock division ratio (1:1/1, 0:1/8)

High:76543210
     |||||||+-- BOOTRST *Refer to data sheet
     |||||++-- BOOTSZ[1:0] *Refer to data sheet
     ||||+-- EESAVE (Retain EEPROM at chip erase 1:No, 0:Yes)
     |||+-- WDTON (1:WDT normal, 0:WDT always on)
     ||+-- SPIEN (1:Disable ISP, 0:Enable ISP) *Available only in Parallel mode
     |+-- JTAGEN (1:Disable JTAG, 0:Enable JTAG)
     +-- OCDEN (On chip debugging 1:Disable, 0:Enable)

Ext: ---4321-
        |+++-- BODLEVEL[2:0]  111:Disabled 110:1.8V 101:2.7V 100:4.3V 011:2.3V
        +-- M161C (1:Native mode, 0:mega161 compatible mode)

;-----------------------------------------------------------------------------;
Device: ATmega165
Mode: ISP/Parallel
Low: 76543210
     ||||++++-- CKSEL[3:0] Clock source selection
     ||++-- SUT[1:0] Startup time
     |+-- CKOUT (0:Output system clock on the CLKO pin)
     +-- CKDIV8 Clock division ratio (1:1/1, 0:1/8)

High:76543210
     |||||||+-- BOOTRST *Refer to data sheet
     |||||++-- BOOTSZ[1:0] *Refer to data sheet
     ||||+-- EESAVE (Retain EEPROM at chip erase 1:No, 0:Yes)
     |||+-- WDTON (1:WDT normal, 0:WDT always on)
     ||+-- SPIEN (1:Disable ISP, 0:Enable ISP) *Available only in Parallel mode
     |+-- JTAGEN (1:Disable JTAG, 0:Enable JTAG)
     +-- OCDEN (On-Chip Debugging via JTAG 1:Disable, 0:Enable)

Ext: ----321-
         |||
         +++-- BODLEVEL[2:0]  111:Disabled, 110:1.8V, 101:2.7V, 100:4.5V

;-----------------------------------------------------------------------------;
Device: ATmega169
Mode: ISP/Parallel
Low: 76543210
     ||||++++-- CKSEL[3:0] Clock source selection
     ||++-- SUT[1:0] Startup time
     |+-- CKOUT (0:Output system clock on the CLKO pin)
     +-- CKDIV8 Clock division ratio (1:1/1, 0:1/8)

High:76543210
     |||||||+-- BOOTRST *Refer to data sheet
     |||||++-- BOOTSZ[1:0] *Refer to data sheet
     ||||+-- EESAVE (Retain EEPROM at chip erase 1:No, 0:Yes)
     |||+-- WDTON (1:WDT normal, 0:WDT always on)
     ||+-- SPIEN (1:Disable ISP, 0:Enable ISP) *Available only in Parallel mode
     |+-- JTAGEN (1:Disable JTAG, 0:Enable JTAG)
     +-- OCDEN (On-Chip Debugging via JTAG 1:Disable, 0:Enable)

Ext: ----3210
         |||+-- RSTDISBL  1:Use RESET pin, 0:Disable RESET(used as PG5)
         +++-- BODLEVEL[2:0]  111:Disabled, 110:1.8V, 101:2.7V, 100:4.5V

;-----------------------------------------------------------------------------;
Device: ATmega8515
Device: ATmega8535
Mode: ISP/Parallel
Low: 76543210
     ||||++++-- CKSEL[3:0] Clock source selection
     ||++-- SUT[1:0] Startup time
     |+-- BODEN (1:Disable BOD, 0:Enable BOD)
     +-- BODLEVEL (1:2.7V, 0:4.0V)

High:76543210
     |||||||+-- BOOTRST *Refer to data sheet
     |||||++-- BOOTSZ[1:0] *Refer to data sheet
     ||||+-- EESAVE (Retain EEPROM at chip erase 1:No, 0:Yes)
     |||+-- CKOPT (Oscillation Mode  1:Low amplitude, 0:Full swing)
     ||+-- SPIEN (1:Disable ISP, 0:Enable ISP) *Available only in Parallel mode
     |+-- WDTON (1:WDT normal, 0:WDT always on)
     +-- S85x5C (1:Native mode, 0:90S compatible mode)

;-----------------------------------------------------------------------------;
Device: ATmega163
Mode: ISP/Parallel
Low: 765-3210
     ||| ++++-- CKSEL[3:0] Clock source selection
     ||+-- SPIEN (1:Disable ISP, 0:Enable ISP) *Available only in Parallel mode
     |+-- BODEN (1:Disable BOD, 0:Enable BOD)
     +-- BODLEVEL (1:2.7V, 0:4.0V)

High:-----210
          ||+-- BOOTRST *Refer to data sheet
          ++-- BOOTSZ[1:0] *Refer to data sheet

;-----------------------------------------------------------------------------;
Device: ATmega323
Mode: ISP/Parallel
Low: 765-3210
     ||| ++++-- CKSEL[3:0] Clock source selection
     ||+-- SPIEN (1:Disable ISP, 0:Enable ISP) *Available only in Parallel mode
     |+-- BODEN (1:Disable BOD, 0:Enable BOD)
     +-- BODLEVEL (1:2.7V, 0:4.0V)

High:76--3210
     ||  |||+-- BOOTRST *Refer to data sheet
     ||  |++-- BOOTSZ[1:0] *Refer to data sheet
     ||  +-- EESAVE (Retain EEPROM at chip erase 1:No, 0:Yes)
     |+-- JTAGEN (1:Disable JTAG, 0:Enable JTAG)
     +-- OCDEN (On-Chip Debugging via JTAG 1:Disable, 0:Enable)

;-----------------------------------------------------------------------------;
Device: ATmega8
Mode: ISP/Parallel
Low: 76543210
     ||||++++-- CKSEL[3:0] Clock source selection
     ||++-- SUT[1:0] Startup time
     |+-- BODEN (1:Disable BOD, 0:Enable BOD)
     +-- BODLEVEL (1:2.7V, 0:4.0V)

High:76543210
     |||||||+-- BOOTRST *Refer to data sheet
     |||||++-- BOOTSZ[1:0] *Refer to data sheet
     ||||+-- EESAVE (Retain EEPROM at chip erase 1:No, 0:Yes)
     |||+-- CKOPT (Oscillation Mode  1:Low amplitude, 0:Full swing)
     ||+-- SPIEN (1:Disable ISP, 0:Enable ISP) *Available only in Parallel mode
     |+-- WDTON (1:WDT normal, 0:WDT always on)
     +-- RSTDISBL (RESET pin 1:Enable, 0:Disable(PC6))

;-----------------------------------------------------------------------------;
Device: ATmega16
Device: ATmega32
Mode: ISP/Parallel
Low: 76543210
     ||||++++-- CKSEL[3:0] Clock source selection
     ||++-- SUT[1:0] Startup time
     |+-- BODEN (1:Disable BOD, 0:Enable BOD)
     +-- BODLEVEL (1:2.7V, 0:4.0V)

High:76543210
     |||||||+-- BOOTRST *Refer to data sheet
     |||||++-- BOOTSZ[1:0] *Refer to data sheet
     ||||+-- EESAVE (Retain EEPROM at chip erase 1:No, 0:Yes)
     |||+-- CKOPT (Oscillation Mode  1:Low amplitude, 0:Full swing)
     ||+-- SPIEN (1:Disable ISP, 0:Enable ISP) *Available only in Parallel mode
     |+-- JTAGEN (1:Disable JTAG, 0:Enable JTAG)
     +-- OCDEN (On-Chip Debugging via JTAG 1:Disable, 0:Enable)

;-----------------------------------------------------------------------------;
Device: ATmega48
Device: ATmega48P
Device: ATtiny43U
Device: ATtiny87
Device: ATtiny167
Mode: ISP/Parallel
Low: 76543210
     ||||++++-- CKSEL[3:0] Clock source selection
     ||++-- SUT[1:0] Startup time
     |+-- CKOUT (0:Output system clock on the CLKO pin)
     +-- CKDIV8 Clock division ratio (1:1/1, 0:1/8)

High:76543210
     |||||+++-- BODLEVEL[2:0] (111:Disabled, 110:1.8V, 101:2.7V, 100:4.3V)
     ||||+-- EESAVE (Retain EEPROM at chip erase 1:No, 0:Yes)
     |||+-- WDTON (1:WDT normal, 0:WDT always on)
     ||+-- SPIEN (1:Disable ISP, 0:Enable ISP) *Available only in Parallel mode
     |+-- DWEN (On-Chip debugging via RESET pin 1:Disable, 0:Enable)
     +-- RSTDISBL (RESET pin 1:Enable, 0:Disable(PC6))

Ext: -------0
            +-- SELFPRGEN *Refer to data sheet

;-----------------------------------------------------------------------------;
Device: ATmega88
Device: ATmega88P
Device: ATmega168
Device: ATmega168P
Mode: ISP/Parallel
Low: 76543210
     ||||++++-- CKSEL[3:0] Clock source selection
     ||++-- SUT[1:0] Startup time
     |+-- CKOUT (0:Output system clock on the CLKO pin)
     +-- CKDIV8 Clock division ratio (1:1/1, 0:1/8)

High:76543210
     |||||+++-- BODLEVEL[2:0] (111:Disabled, 110:1.8V, 101:2.7V, 100:4.3V)
     ||||+-- EESAVE (Retain EEPROM at chip erase 1:No, 0:Yes)
     |||+-- WDTON (1:WDT normal, 0:WDT always on)
     ||+-- SPIEN (1:Disable ISP, 0:Enable ISP) *Available only in Parallel mode
     |+-- DWEN (On-Chip debugging via RESET pin 1:Disable, 0:Enable)
     +-- RSTDISBL (RESET pin 1:Enable, 0:Disable(PC6))

Ext: -----210
          ||+-- BOOTRST *Refer to data sheet
          ++-- BOOTSZ[1:0] *Refer to data sheet

;-----------------------------------------------------------------------------;
Device: ATmega328P
Mode: ISP/Parallel
Low: 76543210
     ||||++++-- CKSEL[3:0] Clock source selection
     ||++-- SUT[1:0] Startup time
     |+-- CKOUT (0:Output system clock on the CLKO pin)
     +-- CKDIV8 Clock division ratio (1:1/1, 0:1/8)

High:76543210
     |||||||+-- BOOTRST (1:Normal, 0:BootLoader)
     |||||++-- BOOTSZ[1:0] (11:256W, 10:512, 01:1024, 00:2048)
     ||||+-- EESAVE (Retain EEPROM at chip erase 1:No, 0:Yes)
     |||+-- WDTON (1:WDT normal, 0:WDT always on)
     ||+-- SPIEN (1:Disable ISP, 0:Enable ISP) *Available only in Parallel mode
     |+-- DWEN (On-Chip debugging via RESET pin 1:Disable, 0:Enable)
     +-- RSTDISBL (RESET pin 1:Enable, 0:Disable(PC6))

Ext: -----210
          +++-- BODLEVEL[2:0] (111:Disabled, 110:1.8V, 101:2.7V, 100:4.3V)

;-----------------------------------------------------------------------------;
Device: ATmega325/9
Device: ATmega3250/90
Device: ATmega645/9
Device: ATmega6450/90
Mode: ISP/Parallel
Low: 76543210
     ||||++++-- CKSEL[3:0] Clock source selection
     ||++-- SUT[1:0] Startup time
     |+-- CKOUT (0:Output system clock on the CLKO pin)
     +-- CKDIV8 Clock division ratio (1:1/1, 0:1/8)

High:76543210
     |||||||+-- BOOTRST *Refer to data sheet
     |||||++-- BOOTSZ[1:0] *Refer to data sheet
     ||||+-- EESAVE (Retain EEPROM at chip erase 1:No, 0:Yes)
     |||+-- WDTON (1:WDT normal, 0:WDT always on)
     ||+-- SPIEN (1:Disable ISP, 0:Enable ISP) *Available only in Parallel mode
     |+-- JTAGEN (1:Disable JTAG, 0:Enable JTAG)
     +-- OCDEN (On-Chip Debugging via JTAG 1:Disable, 0:Enable)

Ext: -----210
          ||+-- RSTDISBL (RESET pin 1:Enable, 0:Disable(PG5))
          ++-- BODLEVEL[1:0] (11:Disabled, 10:1.8V, 01:2.7V, 00:4.3V)

;-----------------------------------------------------------------------------;
Device: ATmega64
Device: ATmega128
Mode: ISP/Parallel
Low: 76543210
     ||||++++-- CKSEL[3:0] Clock source selection
     ||++-- SUT[1:0] Startup time
     |+-- BODEN (1:Disable BOD, 0:Enable BOD)
     +-- BODLEVEL (1:2.7V, 0:4.0V)

High:76543210
     |||||||+-- BOOTRST *Refer to data sheet
     |||||++-- BOOTSZ[1:0] *Refer to data sheet
     ||||+-- EESAVE (Retain EEPROM at chip erase 1:No, 0:Yes)
     |||+-- CKOPT (Oscillation Mode  1:Low amplitude, 0:Full swing)
     ||+-- SPIEN (1:Disable ISP, 0:Enable ISP) *Available only in Parallel mode
     |+-- JTAGEN (1:Disable JTAG, 0:Enable JTAG)
     +-- OCDEN (On-Chip Debugging via JTAG 1:Disable, 0:Enable)

Ext: ------10
           |+-- WDTON (1:WDT normal, 0:WDT always on)
           +-- M103C (1:Native mode, 0:mega603/103 compatible mode)

;-----------------------------------------------------------------------------;
Device: ATmega603
Device: ATmega103
Mode: ISP/Parallel
Low: ----3-10
         | ++-- SUT[1:0] Startup time
         +-- EESAVE (Retain EEPROM at chip erase 1:No, 0:Yes)

;-----------------------------------------------------------------------------;
Device: AT90CAN32
Device: AT90CAN64
Device: AT90CAN128
Mode: ISP/Parallel
Low: 76543210
     ||||++++-- CKSEL[3:0] Clock source selection
     ||++-- SUT[1:0] Startup time
     |+-- CKOUT (0:Output system clock on the CLKO pin)
     +-- CKDIV8 Clock division ratio (1:1/1, 0:1/8)

High:76543210
     |||||||+-- BOOTRST *Refer to data sheet
     |||||++-- BOOTSZ[1:0] *Refer to data sheet
     ||||+-- EESAVE (Retain EEPROM at chip erase 1:No, 0:Yes)
     |||+-- WDTON (1:WDT normal, 0:WDT always on)
     ||+-- SPIEN (1:Disable ISP, 0:Enable ISP) *Available only in Parallel mode
     |+-- JTAGEN (1:Disable JTAG, 0:Enable JTAG)
     +-- OCDEN On-Chip Debugging via JTAG (1:Disable, 0:Enable)

Ext: ----3210
         |||+-- TA0SEL (Must be 1)
         +++-- BODLEVEL[2:0] (111:Off, 110:4.1, 101:4, 100:3.9, 011:3.8, 010:2.7, 001:2.6, 000:2.5)

;-----------------------------------------------------------------------------;
Device: ATmega406
Mode: Parallel
Low: 76543210
     |||||||+-- CKSEL Clock source selection
     |||||++-- SUT[1:0] Startup time
     ||||+-- BOOTRST *Refer to data sheet
     ||++-- BOOTSZ[1:0]
     |+-- EESAVE (Retain EEPROM at chip erase 1:No, 0:Yes)
     +-- WDTON (1:WDT normal, 0:WDT always on)

High:76543210
           |+-- JTAGEN (1:Disable JTAG, 0:Enable JTAG)
           +-- OCDEN (On-Chip Debugging via JTAG 1:Disable, 0:Enable)

;-----------------------------------------------------------------------------;
Device: AT90PWM2/3
Device: AT90PWM216/316
Mode: ISP/Parallel
Low: 76543210
     ||||++++-- CKSEL[3:0] Clock source selection
     ||++-- SUT[1:0] Startup time
     |+-- CKOUT (0:Output system clock on the CLKO pin)
     +-- CKDIV8 Clock division ratio (1:1/1, 0:1/8)

High:76543210
     |||||+++-- BODLEVEL[2:0] (111:Off, 110:4.5, 101:2.7, 100:4.3, 011:4.4, 010:4.2, 001:2.8, 000:2.6
     ||||+-- EESAVE (Retain EEPROM at chip erase 1:No, 0:Yes)
     |||+-- WDTON (1:WDT normal, 0:WDT always on)
     ||+-- SPIEN (1:Disable ISP, 0:Enable ISP) *Available only in Parallel mode
     |+-- DWEN (On-Chip debugging via RESET pin 1:Disable, 0:Enable)
     +-- RSTDISBL (RESET pin 1:Enable, 0:Disable(PC6))

Ext: 7654-210
     |||| ||+-- BOOTRST *Refer to Data Sheet
     |||| ++-- BOOTSZ[1:0] *Refer to Data Sheet
     |||+-- PSCRV PSCOUT Reset Value
     +++-- PSC[2:0]RB PSCn Reset Behaviour

;-----------------------------------------------------------------------------;
Device: ATmega164P
Device: ATmega324P
Device: ATmega324PA
Device: ATmega644P
Device: ATmega644
Device: ATmega640
Device: ATmega1280
Device: ATmega1281
Device: ATmega1284P
Device: ATmega2560
Device: ATmega2561
Mode: ISP/Parallel
Low: 76543210
     ||||++++-- CKSEL[3:0] Clock source selection
     ||++-- SUT[1:0] Startup time
     |+-- CKOUT (0:Output system clock on the CLKO pin)
     +-- CKDIV8 Clock division ratio (1:1/1, 0:1/8)

High:76543210
     |||||||+-- BOOTRST *Refer to data sheet
     |||||++-- BOOTSZ[1:0] *Refer to data sheet
     ||||+-- EESAVE (Retain EEPROM at chip erase 1:No, 0:Yes)
     |||+-- WDTON (1:WDT normal, 0:WDT always on)
     ||+-- SPIEN (1:Disable ISP, 0:Enable ISP) *Available only in Parallel mode
     |+-- JTAGEN (1:Disable JTAG, 0:Enable JTAG)
     +-- OCDEN (On-Chip Debugging via JTAG 1:Disable, 0:Enable)

Ext: -----210
          +++-- BODLEVEL[2:0] (111:Disabled, 110:1.8V, 101:2.7V, 100:4.3V)

;-----------------------------------------------------------------------------;
Device: ATmega325P
Device: ATmega3250P
Mode: ISP/Parallel
Low: 76543210
     ||||++++-- CKSEL[3:0] Clock source selection
     ||++-- SUT[1:0] Startup time
     |+-- CKOUT (0:Output system clock on the CLKO pin)
     +-- CKDIV8 Clock division ratio (1:1/1, 0:1/8)

High:76543210
     |||||||+-- BOOTRST *Refer to data sheet
     |||||++-- BOOTSZ[1:0] *Refer to data sheet
     ||||+-- EESAVE (Retain EEPROM at chip erase 1:No, 0:Yes)
     |||+-- WDTON (1:WDT normal, 0:WDT always on)
     ||+-- SPIEN (1:Disable ISP, 0:Enable ISP) *Available only in Parallel mode
     |+-- JTAGEN (1:Disable JTAG, 0:Enable JTAG)
     +-- OCDEN (On-Chip Debugging via JTAG 1:Disable, 0:Enable)

Ext: -----210
          ||+-- RSTDISBL (RESET pin 1:Enable, 0:Disable(PG5))
          ++-- BODLEVEL[1:0] (11:Disabled, 10:1.8V, 01:2.7V, 00:4.3V)

